1. Field of the Invention
The present invention relates in general to data communications, and more specifically to a system and method which captures and synchronizes an asynchronous signal with unknown length and occurrence to a digital clock having any rate or a variable rate.
2. Description of the Related Art
The time that is needed to generate valid output data provided by an asynchronous analog block varies over process, voltage, and temperature. The output data provided by an asynchronous block must be synchronized with a digital logic clock signal in order for the data to be captured and stored correctly by the digital logic. The clock rate that is used by the digital logic to capture the analog output data, however, varies for different applications. Digital logic which uses a rigid synchronizer design is not able to guarantee capture of spurious and unpredictable analog data when used for different chips using different clock signals, processes, temperatures and voltages. A data ready indicator must be generated and sent to the digital block, and the digital logic that uses this analog data should see the output data earlier than the data ready indicator to provide sufficient setup time. Existing schemes are unable to ensure detection of an asynchronous pulse that is faster than the reference clock used by the digital logic.
It is desired to provide a system and method for capturing valid data provided by an asynchronous analog domain for use by a synchronous domain over a wide range of processes, voltages, temperatures, and clock frequencies, including detecting asynchronous pulses that are faster or slower than the reference clock used within the synchronous domain.